First-in-first-out (FIFO) data structures have been employed in myriad of applications including, for example, very large scale integration (VLSI). Generally, FIFO data structures may be broadly classified as either synchronous or asynchronous.
A synchronous FIFO data structure may be, for example, a FIFO data structure in which a single clock controls the write port and the read port of the FIFO data structure. A typical objective of the synchronous FIFO design is to provide a mechanism for buffering data and subsequently evacuating the buffered data in the order of arrival.
An asynchronous FIFO data structure may be, for example, a FIFO data structure in which a first clock is used to control the write port and a second clock is used to control the read port of the FIFO data structure. The first clock and the second clock may have completely arbitrary phase relationships. In addition to acting as a buffer, the asynchronous FIFO design has been used as a mechanism that reliably transfers data across asynchronous clock domains.
Conventional asynchronous FIFO data structures may be designed for depths of 2n in which n is an integer. However, being restricted to such depths may be the source of a number of inefficiencies. For example, if an application may be optimized for a FIFO depth of 9, then the use of a FIFO data structure with a depth of 24 (i.e., 16) would not fully use all of the available buffer space and would needlessly consume valuable real estate on a printed circuit board or an integrated system (e.g., an integrated chip). The excessive FIFO data structure design may also disrupt stringent fan-out constraints on clock and data signals.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with at least some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.